Power metal-oxide-silicon field-effect transistors (MOSFET) are employed in applications requiring high voltages and high currents. Lateral Power MOSFET devices formed using closed cell or cellular array configuration are sometimes preferred because of their increased channel density, that is, an increased channel width per unit of semiconductor area, which results in reduced on-resistance. Low on-resistance MOSFET devices are desirable for their low power loss and ability to conduct high currents.
FIG. 1 duplicates FIG. 1B of U.S. Pat. No. 7,956,384 and illustrates a lateral MOSFET device formed using cellular transistor array implemented with a polysilicon gate mesh in one example. A cellular transistor array structure is also described in U.S. Pat. No. 5,355,008. As shown in FIG. 1, the square cell array increases the channel width per unit area (W/area) by drawing a mesh of polysilicon lines to form alternating source and drain cells that are connected in parallel by metal strips. Furthermore, by forming the openings in the polysilicon mesh to be in a diamond shape, i.e., having a long diagonal and a short diagonal, the source and drain metal strips, arranged in the direction of the short diagonals, can be made wider, thereby reducing the on-resistance of the transistor without increasing the area of the transistor.
In an NMOS lateral MOSFET device, the transistor typically includes a P-well formed in the substrate as the body of the transistor and heavily doped N+ regions formed in the P-well as the source and drain regions. The body of the NMOS transistor is typically electrically shorted to the source of the transistor. To ensure ruggedness of the lateral MOSFET device, a strong electrical connection between the source and the body of the transistor is desired.
FIG. 2, which includes FIGS. 2(a) and 2(b), illustrates the top and cross-sectional views of a conventional closed cell MOSFET device. Referring to FIG. 2(a), a closed cell MOSFET device 10 is formed using a polysilicon gate mesh 12 defining a cellular array of diffusion regions formed in a well. In the present example, the MOSFET device 10 is an NMOS transistor with N+ diffusion regions formed in a P-well where alternating rows of diffusion regions form the source and drain regions of the transistor. For example, N+ diffusion region 14 forms the source region of the transistor (also referred to as the “source cell”) while N+ diffusion region 16 form the drain region of the transistor (also referred to as the “drain cell”). In this example, the body connection to the source is provided by a P+ body diffusion region 18 formed inside some or all of the source cells. A butting contact 20 is used to electrically connect to both the N+ source region and the P+ body diffusion region. FIG. 2(b) is a cross-sectional view of the cell array of FIG. 2(a) along the line A-A′. Referring to FIG. 2(b), the butting contact 20 is large in size as the contact needs to overlap both the N+ source diffusion region 14 and the P+ body diffusion region 18 in the source cell. The size of the butting contact 20 is larger than the minimally sized contact 17 used to connect to the drain diffusion region 16. The use of butting contacts to form the source/body connection inside a source cell increases the cell pitch of the cellular transistor array which causes an undesirable increase in the on-resistance value of the transistor.
In cases where increasing the cell pitch is not desired, the source and drain cells may be formed using minimum dimensions and the body contacts are formed outside of the cellular transistor array on the periphery of the transistor device. In this case, it is possible to use the minimum contact-to-polysilicon spacing and minimum metal-to-metal spacing to construct the cellular transistor array. However, contacting the body of the transistor only at the periphery of the cellular transistor array results in reduced ruggedness of the transistor device, especially when fast voltage transients are applied across the drain and source terminals of the transistor. This is because the body of the NMOS lateral transistor forms the base of a parasitic bipolar transistor which can get turned on during a fast transient event, leading to thermal runaway that can eventually cause permanent damage to the transistor device.